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Integrated Circuit Systems, Inc.
ICS9148-18
Pentium/ProTM System Clock Chip
General Description
The ICS9148-18 is a Clock Synthesizer chip for Pentium and PentiumPro CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include two CPU and six PCI clocks. One reference output is available equal to the crystal frequency. Additionally, the device meets the Pentium power-up stabilization requirement, acheiving stable CPU and PCI clocks 2ms after power-up. PD# pin can enable a low power mode by stopping crystal OSC and PLL stages. Other power management features include, CPU_STOP# which stops CPU (0:1) clocks, and PCI_STOP# which stops PCICLK (0:4) clocks. High drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 505% duty cycle. The REF clock output typically provides better than 0.5V/ns slew rates. The ICS9148-18 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply.
Features
Generates system clocks for CPU, PCI, plus 14.314 MHz REF0. Supports single or dual processor systems Skew from CPU (earlier) to PCI clock (rising edges for 100/33.3MHz) 1 to 4ns Separate 2.5V and 3.3V supply pins 2.5V or 3.3V output: CPU 3.3V outputs: PCI, REF No power supply sequence requirements Uses external 14.318MHz crystal, no external load cap required for CL=18pF crystal 28 pin 209 mil SSOP
Pin Configuration
Block Diagram
28 pin SSOP
Power Groups
VDD = Supply for PLL core VDD1 = REF0, X1, X2 VDD2 = PCICLK_F, PCICLK (0:4) VDDL = CPUCLK (0:1)
Ground Groups
GND = Ground Source Core GND1 = REF0, X1, X2 GND2 = PCICLK_F, PCICLK (0:4) GNDL = CPUCLK (0:1)
Pentium is a trademark on Intel Corporation. 9148-18 Rev B 07/08/98
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9148-18
Pin Descriptions
PIN NUMBER 26 28 1 2 3, 12 4 5, 7, 8, 10, 11 6, 9 13, 21 14, 20 15 16 17 18 19 25 22 23, 24 27 PIN NAME REF0 GND1 X1 X2 GND2 PCICLK_F PCICLK (0:4) VDD2 VDD GND SEL100/66.6# FS0 PD# CPU_STOP# PCI_STOP# VDDL GNDL CPUCLK (1:0) VDD1 TYPE OUT PWR IN OUT PWR OUT OUT PWR PWR PWR IN IN IN IN IN PWR PWR OUT PWR DESCRIPTION 14.318MHz clock output Ground for REF outputs XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Isolated power for core, nominally 3.3V Isolated ground for core Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Frequency Select pin Powers down chip, active low Halts CPU clocks at logic "0" level when low Halts PCI Bus at logic "0" level when low Power for CPU outputs, nominally 2.5V Ground for CPU outputs. CPU and Host clock outputs @ 2.5V Power for REF outputs.
Select Functions (Functionality determined by FS0 and SEL100/66# pin, see below)
Functionality Tristate Testmode CPUCLK HI - Z TCLK/21 PCI, PCI_F HI - Z TCLK/61 REF0 HI - Z TCLK1
Notes: 1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
SEL 100/66# 0 0 0 0 1 1 1 1
FS0 0 1 0 1
Function Tri-State (Reserved) (Reserved) Active 66.6MHz CPU, 33.3 PCI Test Mode (Reserved) (Reserved) Active 100MHz CPU, 33.3 PCI
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ICS9148-18
Technical Pin Function Descriptions
VDD(1,2) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF0, PCICLK (0:4), and PCICLK_F. This pin operates at 3.3V volts. Clocks from the buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the clocks, please consult the DC parameter table in this data sheet. VDDL This is the power supply for the CPUCLK output buffers. The voltage level for these outputs may be 2.5 or 3.3volts. Clocks from the buffers that this pin supplies will have a voltage swing from Ground to VDDL. For the actual guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this data sheet. GND(1,2) This is the power supply ground (common or negative) return pin for the internal core logic and all the PCI output buffers. GNDL This is the ground for CPUCLK output buffers. X1 This input pin serves one of two functions. When the device is used with a crystal, X1 acts as the input pin for the reference signal that comes from the crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also has an internal Crystal loading capacitor that is connected to ground. With a nominal value of 33pF, no external load cap is needed for a CL=17 to 18pF crystal. X2 This Output pin is used only when the device uses a crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the crystal. The X2 pin also has an internal loading capacitor, nominally 33pF. CPUCLK (0:1) These output pins are the clock outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these clocks is controlled by the voltage level applied to the VDDL pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these clocks and the selection codes to produce them. REF0 The REF Output is fixed frequency clock that runs at the same frequency as the Input Reference Clock or the Crystal (typically 14.31818MHz) attached across X1 and X2. PCICLK_F This Output is equal to PCICLK(0:4) and is FREE RUNNING, and will not be stopped by PCI_STOP#. PCICLK (0:4) These output clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. SELECT 100/66.6MHz# This input pin controls the frequency of the clocks at the CPU & PCICLK output pins. If a logic 1 value is present on this pin, the 100MHz clock is selected. If a logic 0 is used, the 66.6MHz frequency is selected. The PCI clock is multiplexed to run at 33.3MHz for both select cases. PCI is synchronous at the rising edge of PCI to the CPU rising edge (with the skew making CPU early). PD# This is an asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and Crystal are stopped. Power down will also place all the outputs in a low state at the end of their current cycle. The latency of power down will not be greater than 3ms. CPU_STOP# This is a synchronous active low input pin used to stop the CPUCLK clocks in an active low state. All other clocks will continue to run while this function is enabled. The CPUCLKs will have a turn ON latency of at least 3 CPU clocks. PCI_STOP# This is a synchronous active low input pin used to stop the PCICLK clocks in an active low state. It will not effect PCICLK_F nor any other outputs.
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ICS9148-18
Power Management
Clock Enable Configuration
CPU_STOP# X 0 0 1 1 PCI_STOP# X 0 1 0 1 PWR_DWN# 0 1 1 1 1 CPUCLK Low Low Low 100/66.6MHz 100/66.6MHz PCICLK Low Low 33.3 MHz Low 33.3 MHz REF Stopped Running Running Running Running Crystal Off Running Running Running Running VCOs Off Running Running Running Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also. ICS9148-18 Power Management Requirements
SIGNAL SIGNAL STATE Latency No. of rising edges of free running PCICLK 1 1 1 1 3ms 2max
CPU_ STOP# PCI_STOP# PD#
0 (Disabled) 2 1 (Enabled) 1 0 (Disabled) 2 1 (Enabled) 1 1 (Normal Operation)3 0 (Power Down)4
Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF and IOAPIC will be stopped independant of these.
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ICS9148-18
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9148-18. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9148-18. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-18. It is used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-18 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state.
5
ICS9148-18
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internally by the ICS9148-18 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are dont care signals during the power down operations.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
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ICS9148-18
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance Transition Time Settling Time Skew
1 1 1 1 1 1
SYMBOL VIH VIL IIH IIL1 IDD3.0(66) IDD3.3(100) IDD3.3PD Fi CIN CINX Ttrans Ts TSTAB TCPU-PCI1
CONDITIONS
MIN 2 VSS-0.3 -5
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz CL = 0 pF VDD = 3.3 V; All outputs loaded Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V;
0.1 2.0 28 33 100 14.318
MAX UNITS VDD+0.3 V 0.8 V A 5 A 100 100 150 mA A MHz 5 45 3 pF pF ms ms 3 ms ns 4
27
36 5
Clk Stabilization
1.5
3
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current 1 Skew
1
SYMBOL IDD2.5(66) IDD2.5(100) IDD2.5PD tCPU-PCI2
CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF VT = 1.5 V; VTL = 1.25 V
MIN
TYP 3 4
MAX 25 25 100 4
UNITS mA mA A ns
1.5
3
Guaranteed by design, not 100% tested in production.
7
ICS9148-18
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle Jitter, One Sigma Jitter, Absolute
1
SYMBOL RDSP2B
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 13.5 13.5 2
TYP
MAX UNITS 45 45 V V mA mA ns ns % ps ps ps ps
RDSN2B VOH2B VOL2B IOH2B IOL2B tr2B tf2B
1 1 1 1
19
2.3 0.2 -41 37 1.2 1
0.4 -19 1.6 1.6 55 175 250 150 +250
dt2B
45
50 65 140 30
tsk2B
tjcyc-cyc2B tj1s2B
1 1
1
VT = 1.25 V VT = 1.25 V VT = 1.25 V -250
tjabs2B
150
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance
1 1
SYMBOL RDSP5 RDSN5 VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5
1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 20 20 2.6
TYP
MAX UNITS 60 60 Ohm Ohm V V mA mA ns ns % % %
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
16
3.1 0.17 -44 42 0.9 0.8
0.4 -22 4 4 55 3 5
Duty Cycle
45
53 1 3
Jitter, One Sigma Jitter, Absolute
1
tj1s5 tjabs5
1
Guaranteed by design, not 100% tested in production.
8
ICS9148-18
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output Impedance Output Impedance
1 1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1
1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 12 2.6
TYP
MAX UNITS 55 55 V V mA mA ns ns % ps ps ps
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew
1 1 1 1
16
3.1 0.1 -62 57 1.1 1.3
0.4 -22 2 2 55 500 150 250
Duty Cycle
45
50 175 13
Jitter, One Sigma Jitter, Absolute
1
tj1s1 tjabs1
1
-250
120
Guaranteed by design, not 100% tested in production.
9
ICS9148-18
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended.
Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic
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ICS9148-18
SYMBOL MIN. A A1 A2 b c D E e H L N
COMMON DIMENSIONS NOM. 0.073 0.005 0.068 0.012 0.006 See Variations 0.209 0.0256 BSC 0.307 0.030 See Variations 4 MAX. 0.078 0.008 0.070 0.015 0.008 0.212 0.311 0.037 8 0.068 0.002 0.066 0.010 0.004 0.205 0.301 0.025 0
VARIATIONS N 14 16 20 24 28 30 MIN. 0.239 0.239 0.278 0.318 0.397 0.397
D NOM. 0.244 0.244 0.284 0.323 0.402 0.402 MAX. 0.249 0.249 0.289 0.328 0.407 0.407
Dimensions in inches
Ordering Information
ICS9148F-18 ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
Example:
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